您当前的位置: 设计的主要思想是用一个双端口RAM来存储AD采集到的数据，然后再将读地址反着减回来，和对应的ROM里的系数做乘累加后输出给DA。
1 42 //for state mathine 2 43 //============================================================================ 3 44 reg [4:0] state = 5'b0000; 4 45 localparam ram_idle = 5'b00000; 5 46 localparam ram_write = 5'b00001; 6 47 localparam ram_WR_END = 5'b00010; 7 48 // localparam ram_wait = 5'b00100; 8 49 localparam ram_read = 5'b01000; 9 50 localparam state_data_output = 5'b10000; 10 51 reg [15:0]count1; 11 52 reg [15:0]count2; 12 53 reg [15:0]count3; 13 54 reg [15:0]ROM_count; 14 55 reg signed[15:0]ram_output_data; 15 56 reg signed[15:0]rom_output_data; 16 57 always @ (posedge clock or negedge reset_n) 17 58 begin 18 59 if (!reset_n) state <= ram_idle; 19 60 else 20 61 case(state) 21 62 ram_idle : begin 22 63 count1 <= 16'd0; 23 64 count2 <= 16'd0; 24 65 RAM_ADDR_W <= 5'd0; 25 66 RAM_ADDR_R <= 5'd0; 26 67 ROM_ADDR <= 5'd0; 27 68 ram_wr <= 0; 28 69 da_data_ <= 32'd0; 29 70 state <= ram_write; 30 71 end 31 72 ram_write: begin 32 73 if (ad_clk_pos) 33 74 begin 34 75 RAM_ADDR_W <= count1; 35 76 ROM_count <= 5'd0; 36 77 ram_wr <= 1'b1; 37 78 ram_data <= ad_data - 16'd32767; 38 79 da_data_ <= 32'd0; 39 80 if (count1 == 16'd31) begin 40 81 count2 <= count1; 41 82 count3 <= count1 + 1; 42 83 count1 <= 16'd0; 43 84 end 44 85 else begin 45 86 count2 <= count1; 46 87 count3 <= count1; 47 88 count1 <= count1 + 1; 48 89 end 49 90 state <= ram_WR_END; 50 91 end 51 92 end 52 93 ram_WR_END: begin 53 94 ram_wr <= 1'b0; 54 95 state <= ram_read; 55 96 56 97 end 57 98 // ram_wait: begin 58 99 // state <= ram_read; 59 100 // end 60 101 ram_read: begin 61 102 if (ROM_count <= count3) begin 62 103 RAM_ADDR_R <= count2; 63 104 ROM_ADDR <= ROM_count; 64 105 ram_output_data <= ram_output; 65 106 rom_output_data <= rom_output; 66 107 da_data_ <= ram_output_data * rom_output_data + da_data_; 67 108 if (count2 == 0) begin 68 109 69 110 end 70 111 else begin 71 112 count2 <= count2 - 1; 72 113 end 73 114 ROM_count <= ROM_count + 1; 74 115 state <= ram_read; 75 116 end 76 117 else state <= state_data_output; 77 118 end 78 119 state_data_output: begin 79 120 da_data <= da_data_[31:16] + 16'd32767; 80 121 state <= ram_write; 81 122 end 82 123 default: state <= ram_idle; 83 124 endcase 84 125 end
本来我想要在ram_read状态来到时，ROM的地址从0开始累加，RAM的地址从1E开始递减。为什么会多出一个红色圈圈出的地址？求大神帮忙指导下，万分感谢！